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EMC Component Group: A Practical Guide to the Theory, Operation and Selection of Spread Spectrum Clocks.  

A practical guide to the theory,
operation and selection of

Spread Spectrum Clocks


A Spread Spectrum Clock is a special type of digital clock that provides lower EMI output clocks when compared with conventional clock generator outputs. Reducing the amount of EMI radiated from an electronic device is one of the hardest problems to resolve in today’s drive for lower production costs. Producing a compliant device suitable for Class A and Class B consumption can be quite costly if the necessary steps are not taken at design time. Most digital and system design engineers have been formally trained in the area of their expertise and provide a working product but when the product is handed over to the EMC engineer, it soon becomes apparent that the application under test has many EMI problems. It is conceivable that 40 – 50% of the development cost of a new product can be spent in the quest for a compliant product suitable for production.


As stated above, SSC is a technology that provides a lower EMI digital clock for the purpose of achieving regulatory compliance. Also, it is quite obvious that the sooner the EMI problems are tackled and solved the cheaper the product will be to produce.

EMI stands for Electro-Magnetic Interference. If a digital system such as a printer has a fundamental clock frequency of 40 MHz, for example, which would typically drive a processor, memory, serial and USB interfaces and some front panel controls. The original 40 MHz clock probably goes to 1, 2 or 3 components directly before it is changed into other timing components such as clock multipliers found in PLL based processors, memory controllers, interface chips and more. The original 40 MHz quickly becomes 120 MHz or a 20 MHz clock to drive an interface chip. The point is, there are many frequencies being generated from the original system clock in a typical digital design and all of these frequencies are potential problems when it comes to compliance. One more problem to contend with is the fact that every digital signal in the system has an infinite number of harmonics associated with each frequency. In fact, the problem areas that plague a digital system the most are at the higher harmonics of the fundamental frequencies.

If careful thought is not brought into the design phase of the development cycle, it is possible to have a product cancelled simply because the cost of making the system compliant would be far to costly and exceed the development budget. Even after the design phase is done, there will always be hot spots that will require some form of filtering or shielding. Reality sets in when the EMC engineer sees that the agency limits have been exceeded by at least 10 dB in several higher frequency harmonics. When this happens, there are 3 possible ways to solve the problem, re-design in an attempt reduce EMI, filter and shield every net that is offending compliance or replace the original 40 MHz clock with an SSC drop-in replacement clock.

EMI can be reduced on an individual net by slowing down the transition (rise or fall) time of the digital signal. The easiest way to slow down the rise time of a digital signal is to add capacitance to the net at the source end of the net. This will force the driver to source current into the capacitor as well as supplying current to the load, which in turn reduces the rise time and fall time of the signal. Figures 1 and 2 show the result of slowing down the rise time of a digital signal.

Figure 1.

Figure 1 shows that the rise time of this signal has gone from 1.705 ns. to 7.384 ns. by adding more capacitance to the net in an attempt to reduce EMI.

Figure 2.

It is difficult to see, but the spectrum analyzer indicates the signal strength reduction on this net is 0.8 dB. This is not much of a reduction in signal strength for such a drastic increase in rise time and this solution only affects one net. To effectively reduce EMI across the entire system using this method, each hot spot would have to be identified and an additional capacitor added to the circuit. This approach would be very costly in terms of rework time and component cost.

A much better approach to reducing EMI would be to use a Spread Spectrum Clock which reduces the radiated energy without the need to slow down the rise and fall times of digital signals.

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